Transient suppression with lossless steady state operation

ABSTRACT

A power supply efficiently suppresses transient voltages by storing the maximum charge expected in the transient and releasing it during the transient event at a rate in an equal but opposite amount to the transient, preventing the battery voltage from collapsing. The described power supply provides improved efficiency compared to conventional architectures for transient suppression, thus increasing the length of time between battery charges and creating a better user experience.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §120 as a continuation of U.S. patent application Ser. No. 14/207,292 filed on Mar. 12, 2014, titled “Transient Suppression with Lossless Steady State Operation,” which claims the benefit of U.S. Provisional Patent Application No. 61/780,192 filed on Mar. 13, 2013, titled “Transient Suppression with Lossless Steady State Operation.” Each of these applications is herein incorporated by reference in its entirety.

BACKGROUND

1. Field of Technology

Embodiments disclosed herein relate to power supplies, and more specifically to managing transient load currents in a power supply.

2. Description of the Related Arts

Modern mobile devices such as laptops, smartphones and tablets typically include a re-chargeable battery to power the electronics inside. The batteries are often kept as small as possible in order to make the mobile device smaller and lighter. As a consequence, these batteries have finite capacity and a finite ability to deliver current to the load.

A battery's ability to deliver current is quantified by the internal resistance of the battery. When the battery is not connected to any loading circuit, it will show a particular voltage across its terminals called the “open circuit voltage.” When a loading circuit is connected to the battery, current flows from the battery through the loading circuit. This increase in current causes the voltage across the terminals of the battery to droop below its open circuit voltage. Batteries with a larger internal resistance will produce a larger voltage droop for a given load current.

These load currents may be particularly large in modern electronic devices that include multiple circuits operating from a single battery, such as for example, application processors, digital baseband processors, image processors, etc. During start up or under other transient conditions that produce large current drains from the battery, the battery's voltage may fall until the voltage is no longer sufficient to sustain the operation of the loading circuits, causing the entire device to reset.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the embodiments disclosed herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram illustrating a first embodiment of a load transient suppression circuit.

FIG. 2 is a waveform diagram illustrating example waveforms associated with operation of a load transient suppression circuit.

FIG. 3 is a circuit diagram illustrating a second embodiment of a load transient suppression circuit.

DETAILED DESCRIPTION

The Figures (FIG.) and the following description relate to various embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles discussed herein.

Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict various embodiments for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.

A power supply efficiently suppresses transient voltages by storing charge and releasing the charge during the transient event at a rate in a substantially equal but opposite amount to the transient, preventing the battery voltage from collapsing. In one embodiment, the stored charge comprises a maximum amount of charge expected in the transient, or a charge within a predefined range of this expected maximum. The described power supply provides improved efficiency compared to conventional architectures for transient suppression, thus increasing the length of time between battery charges and creating a better user experience.

FIG. 1 illustrates a first embodiment of a load transient suppression circuit 120 coupled in parallel with a battery 110 and an electronic device 130. Battery 110 is represented in FIG. 1 as a voltage source 102 that produces a voltage Vo and an internal resistor R4, resulting in an overall battery voltage Vdd coupled to electronic device 130. Load transient suppression circuit 120 ensures that voltage Vdd does not drop below a threshold voltage (e.g., a minimum operating voltage of electronic device 130) during transient load conditions.

The load transient suppression circuit 120 comprises an operational amplifier X1, capacitors C3-C4, resistor R3, and an operational amplifier input circuit 140 including capacitors C1-C2, resistors R1-R2 and voltage subtraction circuit 104. Operational amplifier input circuit 140 produces differential voltage V+, V− provided to the operational amplifier X1 to supply a positive differential voltage under transient conditions and a negative differential voltage under nominal conditions. Voltage subtraction circuit 104 can be implemented using any conventional technique, such as, for example, a differential amplifier in a voltage subtraction configuration. During nominal load conditions, voltage V+ at the positive input node of operational amplifier X1 is below voltage V− of the negative input node due to the voltage drop V1. Thus, the output of operational amplifier X1 is railed to ground (e.g., Vout=0V) during nominal conditions. Thus, during nominal conditions, operational amplifier X1 does not deliver or consume any current other than its bias current. The supply terminal of operational amplifier X1 receives a supply voltage Vcc. The supply voltage Vcc approaches Vdd under nominal conditions and both C4 and C3 are charged to approximately Vdd. Assuming R4 is small, Vdd is approximately Vo.

Under transient conditions when device current lout spikes up, voltage Vdd will start to drop due to the internal resistance R4 of battery 110. This causes voltage V− at the negative input node of operational amplifier X1 and V+ at the positive input node to drop at respective rates related to the respective time constants of R₁C₁ and R₂C₂. The values of resistor R1, R2 and capacitors C1, C2 are selected such that τ₁=R₁C₁<<τ₂=R₂C₂, where τ₁ is the RC time constant of resistor R1 and capacitor C1 coupled to the negative input node of operational amplifier X1, and τ₂ is the RC time constant of resistor R2 and capacitor C2 coupled to the positive input node of operational amplifier X1. Due to the difference in time constants, voltage V− at the negative input node of the operational amplifier X1 drops faster than voltage V+ at the positive input node of the operational amplifier X1, and V− drops below V+. This causes output voltage Vout of operational amplifier X1 to rise above 0V during transient load conditions. Vdd is then pushed back up as current starts flowing through capacitor C3 via Vout.

The current from operational amplifier X1 come from the power supply voltage Vcc of operational amplifier X1. To supply this current, C4 starts discharging. Resistor R3 ensures that the current flowing from C3 boosts Vdd and does not charge C4. C3 and C4 will continue to sustain the output voltage at Vdd until both capacitors are roughly Vo/2 (assuming C3=C4). The values of C3 and C4 are selected such that the voltages across them do not reach Vo/2 until the end of the transient period. Once the transient period ends, capacitors C3 and C4 slowly charge back to approximately Vo.

To achieve the desired functionality, R3 is generally larger than R4. If R3 is too small, charge pumped out by capacitor C3 may be dissipated in large portion by resistor R3. However, if R3 is large compared to R4, then most of the charge from capacitor C3 will flow to device 130. However, a larger value of R3 will increase the time it takes to recharge capacitor C4 after the transient event. Thus, the exact value of R3 may be determined based on the desired tradeoffs.

FIG. 2 illustrates example waveforms representing operation of load transient suppression circuit 120 of FIG. 1. In this example, battery 110 produces a voltage of Vo=3V and has a internal resistance of R4=0.5 ohms under transient conditions. Under nominal conditions, electronic device 130 draws a current lout of 100 mA, resulting in Vdd=2.95V. At a time t₁, load current lout spikes up to 5A which causes Vdd to begin to drop. The drop in Vdd causes voltage V+ to rise above voltage V−, which in turn causes Vout to begin to rise. The rise in Vout stabilizes Vdd and prevents Vdd from dropping further. Particularly, the rising Vout increases current through capacitor C3 during the transient condition (between time t₁ and time t₂ in FIG. 2). C3 furthermore discharges to provide current to device 130 and prevent Vdd from collapsing. Vcc also drops between t₁ and t₂ as C4 discharges. At time t₂, the transient period ends and output current lout drops back down to 100 mA. When this occurs, C3 and C4 begin to charge back up, thus causing Vout to drop and Vcc to increase back up to approximately 3V. Vdd rises back up to approximately 3V once Vout reaches approximately 0V and capacitor C3 is fully charged at time t₃.

The total capacitance of C3 and C4 are selected such that such that the transient voltage Vdd is always above a minimum operating voltage of electronic device 130 for a given battery voltage. For instance, in the example above a total capacitance of 700 μF (e.g., C3=C4=350 g) will ensure that Vdd remains above 2.7V for a 3V battery.

FIG. 3 illustrates an alternative embodiment of a load transient suppression circuit 320. In this embodiment, resistor R3 is replaced with a switch S1 (e.g., a transistor) that is controlled based on the detection of a transient event, but otherwise the embodiment of FIG. 3 is similar to that of FIG. 2. In one embodiment, a sense circuit 322 senses a transient event by monitoring voltage Vdd or current lout. For example, sense circuit 322 detects a transient condition when Vdd drops below a threshold voltage or when a magnitude of a rate of change of Vdd exceeds below a threshold rate. Alternatively, sense circuit 322 may detect the transient condition when lout rises about a threshold current or when a magnitude of a rate of change of lout rises above a threshold rate. In response to detecting the transient condition, sense circuit 322 turns switch S1 off, thus causing the Vcc node of operational amplifier X1 to draw current from capacitor C4. When sense circuit senses 322 that the transient condition ends, switch S1 is turned back on. Switch S1 remains on during nominal conditions, thus allowing capacitor C4 to charge back up to approximately Vdd.

Upon reading this disclosure, those of skill in the art will appreciate still additional alternative designs for a load transient suppression circuit. Thus, while particular embodiments and applications have been illustrated and described, it is to be understood that the embodiments discussed herein are not limited to the precise construction and components disclosed herein and that various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope of the disclosure. 

1. A transient suppression circuit, comprising: a power supply terminal configured to couple to a voltage source and to an electronic device to provide power to the electronic device; an operational amplifier having an output coupled to the power supply terminal to provide an output current during a transient load condition; and a bias capacitor, coupled to a bias input of the operational amplifier, to discharge and provide a bias current to the operational amplifier during the transient load condition.
 2. The transient suppression circuit of claim 1 further comprising an output capacitor coupled between the output of the operational amplifier and the power supply terminal to provide a discharge current to the electronic device during the transient load condition to prevent the power supply terminal from dropping below a threshold voltage.
 3. The transient suppression circuit of claim 2 wherein the bias capacitor and output capacitor are configured to collectively store an amount of charge during the nominal load condition based on an expected maximum drop in a voltage at the power supply terminal during the transient load condition and an expected maximum duration of the transient load condition.
 4. The transient suppression circuit of claim 1 further comprising an operational amplifier input circuit to provide a first voltage to a positive input terminal of the operational amplifier and to provide a second voltage to a negative input terminal of the operational amplifier, the second voltage being greater than the first voltage during a nominal load condition and the second voltage dropping below the first voltage in response to the transient load condition to cause the operational amplifier to provide the output current during the transient load condition.
 5. The transient suppression circuit of claim 4 wherein the operational amplifier input circuit includes a first RC circuit having a first time constant, the first RC circuit coupled to the power supply terminal, and the first RC circuit to provide the first voltage to the positive terminal of the operational amplifier; and a second RC circuit having a second time constant, the second RC circuit coupled to the power supply terminal, and the second RC circuit to provide the second voltage to the negative terminal of the operational amplifier.
 6. The transient suppression circuit of claim 1 further comprising a switch to couple the power supply terminal to the bias input of the operational amplifier during the nominal load condition and to decouple the power supply terminal from the bias input during the transient load condition.
 7. The transient suppression circuit of claim 1 further comprising a resistor coupled between the power supply terminal and the bias input of the operational amplifier.
 8. A transient suppression circuit, comprising: a power supply terminal configured to couple to a voltage source and to an electronic device to provide power to the electronic device; an operational amplifier having an output coupled to the power supply terminal to provide an output current during a transient load condition; a bias capacitor, coupled to a bias input of the operational amplifier, to discharge and provide a bias current to the operational amplifier during the transient load condition; and a current limiting element, coupled between the power supply terminal and the bias input of the operational amplifier, to limit an amount of current flowing from the power supply terminal to at least one of the bias input of the operational amplifier and the bias capacitor during the transient load condition.
 9. The transient suppression circuit of claim 8 further comprising an output capacitor coupled between the output of the operational amplifier and the power supply terminal to provide a discharge current to the electronic device during the transient load condition to prevent the power supply terminal from dropping below a threshold voltage.
 10. The transient suppression circuit of claim 9 wherein the bias capacitor and output capacitor are configured to collectively store an amount of charge during the nominal load condition based on an expected maximum drop in a voltage at the power supply terminal during the transient load condition and an expected maximum duration of the transient load condition.
 11. The transient suppression circuit of claim 8 further comprising an operational amplifier input circuit to provide a first voltage to a positive input terminal of the operational amplifier and to provide a second voltage to a negative input terminal of the operational amplifier, the second voltage being greater than the first voltage during a nominal load condition and the second voltage dropping below the first voltage in response to the transient load condition to cause the operational amplifier to provide the output current during the transient load condition.
 12. The transient suppression circuit of claim 11 wherein the operational amplifier input circuit includes a first RC circuit having a first time constant, the first RC circuit coupled to the power supply terminal, and the first RC circuit to provide the first voltage to the positive terminal of the operational amplifier; and a second RC circuit having a second time constant, the second RC circuit coupled to the power supply terminal, and the second RC circuit to provide the second voltage to the negative terminal of the operational amplifier.
 13. The transient suppression circuit of claim 8 wherein the current limiting element is a switch.
 14. The transient suppression circuit of claim 8 wherein the current limiting element is a resistor.
 15. A transient suppression circuit for providing power to an electronic device, comprising: a power supply terminal configured to couple to a voltage source and to the electronic device to provide power to the electronic device; an operational amplifier to receive a differential input voltage and produce an output current responsive to the differential input voltage being positive; an operational amplifier input circuit to provide the differential input voltage to the operational amplifier, the differential input voltage being positive during a transient load condition, and the differential input voltage being negative during a nominal load condition; and a bias capacitor coupled to a bias input of the operational amplifier to supply a bias current to the bias input of the operational amplifier during the transient load condition to enable the operational amplifier to supply the output current.
 16. The transient suppression circuit of claim 15 further comprising an output capacitor coupled between an output of the operational amplifier and the power supply terminal to supply a discharge current to the electronic device in response to the output current produced by the operational amplifier during the transient load condition, the discharge current sufficient to prevent the power supply terminal from dropping below a threshold voltage.
 17. The transient suppression circuit of claim 16 wherein the bias capacitor and output capacitor are configured to collectively store an amount of charge during the nominal load condition based on an expected maximum drop in a voltage at the power supply terminal during the transient load condition and an expected maximum duration of the transient load condition.
 18. The transient suppression circuit of claim 15 wherein the operational amplifier input circuit provides the differential input voltage to the operational amplifier by providing a first voltage to a positive input terminal of the operational amplifier and providing a second voltage to a negative input terminal of the operational amplifier, the second voltage being greater than the first voltage during a nominal load condition and the second voltage dropping below the first voltage in response to the transient load condition.
 19. The transient suppression circuit of claim 15 further comprising a switch to couple the power supply terminal to the bias input of the operational amplifier during the nominal load condition and to decouple the power supply terminal from the bias input during the transient load condition.
 20. The transient suppression circuit of claim 15 further comprising a resistor coupled between the power supply terminal and the bias input of the operational amplifier. 